1. Field of the Invention
The present invention relates to a power plane system of high-speed digital circuit, more particularly, a power plane system of high-speed digital circuit for suppressing ground bounce noise.
2. Description of the Related Art
The related prior art has been disclosed in U.S. Pat. Nos. 6,084,779, 6,557,154 and 6,518,930.
In high-speed digital circuit, signal line connects to the power plane, and there are parasitic inductance, capacitance and resistance. When the integrated circuit rapidly switches, a temporary voltage (ΔV) is produced between the power plane. The temporary voltage is a noise known as ground bounce noise (GBN). The resonance mode excited by the ground bounce noise causes significant signal integrity (SI) problem and electromagnetic interference (EMI) issues.
Two conventional techniques are utilized to decrease the influence of the ground bounce noise. Firstly, adding decoupling capacitors to create a low impedance path between the power and ground planes is a typical way to suppress the ground bounce noise.
Secondly, referring to FIG. 1, the conventional power plane system 10 comprises a substrate 11, a power layer 12 and a ground layer 13. The power plane 12 is formed on a first surface of the substrate 11, and the ground layer 13 is formed on a second surface of the substrate 11. The power layer 12 is a metal plate 121 having a slit 122. The slit 122 defines a region 123 to limit the ground bounce noise within the region 123. Therefore, the ground bounce noise within the region 123 does not affect the elements outside the region 123. Besides, the slit 122 is cut to decrease the area of the metal plate 121 so that the resonance frequency of electromagnetic radiation is shifted to a high frequency band, and good noise suppression and low electromagnetic radiation field in the operation frequency can be obtained.
Nevertheless, in the first conventional technique, the adding decoupling capacitor has a parasitic inductance. The more capacitance of the decoupling capacitor there is, the more parasitic inductance there is. Therefore, the suppression effect will decrease because of high parasitic inductance. In the second conventional technique, if there is no a channel 124 on the slit 122, the voltage level is cut and the signal line should cross the slit to connect with the other elements so as to cause serious signal integrity (SI) problem and electromagnetic interference (EMI) issues. It is necessary to have a channel 124 on the slit 122 to hold the voltage level and prevent signal line from crossing the slit 122. However, according to the experiment, the channel 124 will decrease the effect for suppressing noise and electromagnetic radiation and produce a new resonance frequency in the low frequency band.
Referring to FIG. 2, another conventional power plane system 20 is utilized to suppress the ground bounce noise. The conventional power plane system 20 comprises a substrate 21, a first power layer 22 and a second power layer 23. An integrated circuit 24 is disposed on the second power layer 23, and receives power from the first power layer 22. When the integrated circuit 24 rapidly switches and induces the ground bounce noise on the first power layer 24, a plurality of umbrella structures 26, 27, 28, 29 are utilized to suppress the ground bounce noise to zero. However, the umbrella structures 26, 27, 28, 29 are mounted in the substrate 21 to raise the height of the substrate and the complexity in manufacture.
Therefore, it is necessary to provide a source driver so as to solve the above problem.